Electromagnetic radiation imaging device using dual gate thin film transistors

ABSTRACT

An electromagnetic radiation imaging device comprising an energy absorbing layer overlying an array of thin film transistors (TFTs). each of the thin film transistors incorporates a dual gate. The lower gate provides row selection, while the upper gate of the same device modulates current conducted by the transistor. By utilizing dual gates, a reduction in the number of transistors is achieved over prior art imaging devices, thereby increasing production yield. Furthermore, the use of dual gate transistors provides increased versatility in choosing the bias point of the transistors.

FIELD OF THE INVENTION

This invention relates in general to opto-electronic devices, and moreparticularly to an electromagnetic radiation imaging deviceincorporating an array of dual gate thin film transistors.

BACKGROUND OF THE INVENTION

The use of two-dimensional arrays of thin film transistors for radiationdetection is known in the art. One prior art X-ray imaging detector hasbeen developed at the University of Michigan, as described in L. E.Antonuk, J. Boudry, W. Huang, D. L. McShan, E. J. Morton, J. Yorkston,M. J. Longo, and R. A. Street, Multi-Element Amorphous Silicon DetectorArray (MASDA), MED PHYS 19, 1455 (1992). In this prior art detector, ascintillating material (e.g. phosphor screen or CsI) converts X-raysdirectly into light. The light then impinges on an array of a-Si:Hphotodiodes, which produce charge in proportion to the light intensity.The generated charge is stored on a capacitor and is read out through athin film transistor (TFT) as each line is addressed.

Another prior art detector has been developed by researchers at theUniversity of Toronto in which X-rays are converted directly to charge.This system is described in W. Zhao and J. S. Rowlands, Selenium ActiveMatrix Universal Read-out Array Imager (SAMURAI), Medical Imaging VII:Physics of Medical Imaging SPIE (1993). Both the prior art MASDA andSAMURAI devices require measurement of charge (or integrated current),which is proportional to X-ray intensity, for each addressed row of thearray.

Instead of directly measuring the charge generated by the radiation, itis known in the art to allow the charge to accumulate on the gate of afield effect transistor and to modulate the current through the channel.This approach takes advantage of the intrinsic amplification function ofa field effect transistor and also allows the signal to be measuredwithout necessarily destroying the charge. This prior art approach toradiation detection has been disclosed in U.S. Pat. Nos. 5,182,624 and5,235,195 (Tran et al).

A modified version of this approach, for video camera use, has also beenproposed (see Z-S. Huang and T. Ando, IEEE Transactions on ElectronicDevices, ED-37 1432 (1990) and F. Andoh, K. Taketoshi, J. Yamasaki, M.Sugawara, Y. Fujita, K. Mitani, Y. Matuzawa, K. Miyata and S. Araki,Proceedings of IEEE International Solid State Circuits Conference, page212 (1990)). In this modified version, a three transistor circuit isused at each pixel location. One of the transistors is used for rowselection, another is used for modulating the current in proportion tothe radiation-induced charge, and third transistor is used to clear theradiation-induced charge when the next row is addressed.

SUMMARY OF THE INVENTION

According to the present invention an electromagnetic radiation imagingdetector is provided comprising an energy absorbing layer overlying anarray of thin film transistors. Electron-hole pairs (EHPs) are generatedin the energy absorbing layer in proportion to the intensity ofelectromagnetic radiation to which the layer is exposed. A voltage isapplied across the absorbing layer for separating the electron-holepairs. According to the present invention, each of the thin filmtransistors incorporates a dual gate. The lower gate is used for rowselection in the array, and the upper gate is used to collect chargegenerated by the energy absorbing layer. This charge effectivelymodulates the current conducted by each thin film transistor so thatupon addressing individual rows of pixels, the drain currents from theassociated thin film transistors may be measured to provide an accuratereading of the electromagnetic radiation in the vicinity of the pixel.

The composition of the energy absorbing layer is chosen for sensitivityin the desired region of the electromagnetic spectrum. The energyabsorbing layer may comprise a single layer material, or a multi-layerstack, as in a PIN photodiode. A list of suitable materials for variousspectral regions is disclosed in U.S. Pat. No. 5,235,195 (Tran et al).The energy absorbing layer may be a uniform coating or may be delineatedto form isolated devices on each pixel.

According to the preferred embodiment, in addition to the signalmodulated thin film transistor, each pixel includes a further transistorwhich is used to clear the charge on the upper gate through the drainlines when the next row of the array is addressed.

By reducing the number of transistors required for each pixel over theabove-discussed prior art systems, significant advantages are enjoyedover the prior art in terms of production yield. Furthermore, the dualgate thin film transistors of the present invention provide greaterversatility in the ability to choose the bias point of thesignal-modulated transistor. In particular, for pixel arrays whichutilize only single gate field effect-transistors, the threshold voltageof all transistors is fixed by the fabrication technology. By way ofcontrast, the threshold voltage measured with respect to one gate in adual gate TFT may be altered by changing the bias of the other gate.Thus, according to the present invention it is possible to performradiation measurements with a single ON state value of the lower gatevoltage, or to sweep the lower gate voltage and utilize the mostsensitive bias point for each pixel, or the bias point with the mostlinear response.

BRIEF DESCRIPTION OF THE DRAWINGS

A detailed description of the preferred embodiment is provided hereinbelow with reference to the following drawings in which:

FIG. 1 is a circuit diagram of an electromagnetic radiation imagingdevice according to the present invention;

FIG. 2 is a cross-sectional view of a single pixel element of theimaging device of FIG. 1 with top contact implementation, according to afirst embodiment of the invention;

FIG. 3 is a cross-sectional view of a single pixel element of theimaging device of FIG. 1 with bottom contact implementation, accordingto a second embodiment of the invention;

FIG. 4 is a perspective view of a single pixel element (without energyabsorbing layer and top electrode) with top gate metal on the same levelas source and drain, according to a further embodiment of the invention;

FIG. 5. is a timing diagram for operation of the device of FIGS. 1 to 4;

FIG. 6 is a graph showing drain current as a function of one gatevoltage with opposite gate voltage as a parameter for a dual gate TFTaccording to the present invention;

FIG. 7 is a circuit diagram of an imaging device without clearingtransistor, according to a further alternative embodiment; and

FIG. 8 is a circuit diagram of an imaging device with top gate chargecleared to source lines according to yet another alternative embodimentof the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Turning to the circuit diagram of FIG. 1, an electromagnetic radiationimaging device is illustrated comprising an array of pixels 11, eachcomprising a signal modulation transistor 13, a charge clearingtransistor 15 and a radiation to charge transducer 51, schematicallyrepresented by a photodiode. In the illustrated embodiment, 2 by 4pixels are shown, although in practice, arrays on the order of 640×480pixels or greater are contemplated.

Each of the TFTs 13 and 15 is a dual gate transistor comprisingrespective lower gates 27 and 29, as discussed in greater detail belowwith reference to FIG. 2-4, and a shared upper gate 41.

The lower gate 27 of each signal modulating TFT 13, is connected to arow select line 17 to which a bottom gate voltage V_(GB) of V_(ON) orV_(OFF) is applied by a vertical scanner 52. In response to applicationof the V_(ON) signal on a predetermined one of the row select lines 17,the row of transistors 13 connected to that line is enabled. The row oftransistors 13 connected to a row select line 17 to which a V_(OFF)voltage is applied, is disabled. Thus, by selectively applying theV_(ON) voltage to successive ones of the row select lines 17, respectiverows of the array are enabled. Likewise, the charge clearing transistor15 for each pixel is enabled immediately following selection of the rowto which its associated signal modulating transistor 13 has beenselected, for clearing charge on the upper gate 41 as discussed ingreater detail below.

Each of the source electrodes 38 of respective ones of signal modulatingTFTs 13 are connected to respective data columns 19 which are connectedto current measurement devices 21. The drain electrodes 39 oftransistors 13 and 15 are connected together and to an output voltageline 23 (V_(D)).

The current measurement devices 21 can be operational amplifiersconfigured for current measurement, analogue-to-digital converters, orsuitable well known current measurement means.

Turning now to FIGS. 2 and 3, cross sectional views of two embodimentsof a single pixel element are shown according to the present invention.The array of transistors 13 and 15 are disposed on a suitable substrate25 such as glass. Next, the lower gates 27 and 29 are deposited fortransistors 13 and 15, respectively. A first insulating layer 31 isdeposited over the gate electrodes 27 and 29 and semiconductor channelregions 33 and 35 are created for transistors 13 and 15, respectively,using conventional techniques. A second insulating layer 37 is thendeposited on semiconductor channel regions 33 and 35.

According to the embodiment of FIG. 3, source and drain contacts 38 and39 contact semiconductor channel regions 33 and 35 at the bottomthereof, whereas in the embodiment of FIG. 2, the source and draincontacts 38 and 39 contact the semiconductor channel regions 33 and 35at the top thereof. In the top contact embodiment of FIG. 2, anadditional insulating layer 40 is provided intermediate layers 31 and37. This insulation layer is optional and may be reduced to zerothickness.

The charge collecting upper gate 41 is deposited over insulating layer37 and is shared by both transistors 13 and 15.

Next, electromagnetic energy absorbing layer 43 is deposited over theupper gate 41 and a top electrode 45 is deposited on the energyabsorbing layer 43. The top electrode 45 must be transparent orsemi-transparent in the desired spectral region to be detected. Suitableelectrode materials include thin metal films for X-ray detection andindium tin oxide (ITO) for visible light detection.

As discussed above, the composition of the energy absorbing layer 43must be chosen for sensitivity in the desired region of theelectromagnetic spectrum. For example, selenium may be used for X-raydetection, an amorphous silicon PIN stack may be used for visible lightdetection.

A variety of semi-conductor materials may be used for the regions 33 and35, including amorphous and polycrystalline silicon, and CdSe.

The contact metalization 38 and 39, insulating layers 31, 37 and 40, andthe substrate 25 may be formed using a wide variety of materials ormaterial composites well known in the semiconductor industry.

In the embodiment of FIG. 4, the upper gate 41 is shown deposited on thesame level as the source line 38 and drain line 39. The energy absorbinglayer and high voltage top electrode have been omitted from FIG. 4 forvisual clarity. In FIG. 4, contact vias are shown for connecting variouselectrodes of the thin film transistors, as follows: 47 is a contact viato the source of signal modulating transistor 13; 48 is a contact via tothe drain of transistor 13; 49 is a contact via to the drain of chargeclearing transistor 15; and 50 is a contact via from the upper gate 41to the source electrode of transistor 15.

Turning now to FIG. 5 in combination with FIGS. 1-4, operation of theelectromagnetic radiation detector of the present invention isdescribed. The timing diagram of FIG. 5 shows voltages applied to therow select lines 17 of respective rows of the TFT array (FIG. 1). Thus,at time T₁, a voltage V_(ON) is applied to the first row of the arrayfor measuring current on respective data columns 19 through respectivecurrent measurement devices 21 for the selected row. More particularly,in response to being exposed to electromagnetic radiation, electron-holepairs (EHPs) are generated in the energy absorbing layer 43. A highvoltage applied to top electrode 45 causes charge carriers of onepolarity to drift upwardly toward the top electrode and charge carriersof the opposite polarity to be collected on the upper gate 41. Thus,with transistor 13 in the ON state as a result of the V_(ON) voltagebeing applied to lower gate 27, current conducted between the drain andsource of TFT 13 is modulated by the electric field generated as aresult of charge collected and stored on upper gate 41. In other words,the deposited charge on gate 41 acts as a gate voltage to modulate thecurrent through semiconductor channel 33.

At time t₂, the current flowing in the second row of pixels is measuredand the charge stored on upper gate 41 of the first row of transistorsis discharged by enabling TFT 15 associated with each such pixel. Thus,transistor 15 is only used to clear the charge from the upper gate 41after measuring current flowing in the associated transistor 13.

At time t₃, the current in the first row of transistors is measuredagain with signal charge absent from upper gate 41. At time t₄, thecurrent in transistors 13 for the first row is measured again withsignal charge absent but with an increased lower gate voltage on lowergate 27.

At time t₅, the current flowing in TFTs 13 for the third row is measuredwith signal charge present while the signal charge is cleared from theupper gate 41 in each transistor of the second row. The identicalpattern is continued for times t₆, t₇ . . . etc.

The signal on the first row of transistors, resulting from chargedeposited on the top gate 41, can be represented by an equivalent changein the voltage on lower gate 27 (ΔV_(b)), given by: ##EQU1##

This formula takes into account both the zero signal offset anddevice-to-device variations in transistor gain assuming that for eachdevice, the gain measured with respect to the top gate 41 is a constantfraction of the gain measured with respect to the lower gate 27.Device-to-device variations which are disproportionate between upper andlower gates cannot be factored out.

Other measurement schemes for data readout are also possible. Forexample, if the array has little device-to-device gain variation, the t₄measurement can be omitted and the desired signal is simply thedifference I_(d) (t₁)-I_(D) (t₃).

Another possibility is to drive the selected row with a voltage ramp anduse a comparator in the current measurement circuit to identify thelower gate voltage which produces a designated current. This voltagewould vary with the inducted potential on the top gate.

As discussed above, by utilizing dual gate TFTs in the presentinvention, the threshold voltage measured with respect to one gate (27or 41) may be altered by changing the bias of the other gate (41 or 27),see for example J-P. Colinge, IEEE Electron Dev. Lett. EDL-6, 573(1985), and H. K. Lim and J. G. Fossum, IEEE Transactions on ElectronicDevices 30, 1244 (1983). This effect is illustrated in FIG. 6, whichshows the drain current as a function of one gate voltage, with theother gate voltages as a parameter. The device on which the measurementsof FIG. 6 were performed was a CdSe TFT.

As discussed above, with the dual gate structure of the presentinvention, it is possible to perform measurements with a single ON statevoltage of the lower gate 27 voltage, or to sweep the lower gate voltageand utilize the most sensitive bias point for each pixel. By makingmeasurements with more than one ON state value, it is also possible tocheck the gain of each TFT 13 and digitally compensate fordevice-to-device variations (this assumes that the rate of change ofI_(D) with the lower gate voltage is related in a simple way to the rateof change of I_(D) with signal charge).

For the FIG. 3 embodiment of the present invention, the transistor 15provides protection against the possible build-up of destructive chargeon the top gate electrode 41. Even with the lower gate voltage set to anominally OFF value, the excess charge will eventually turn ONtransistors 15, thereby draining the charge and providing a saturationlimit. The saturation level depends on the refresh rate and themagnitude of the bottom gate bias used to turn OFF the TFTs 13. CdSeTFTs are particularly flexible in this regard, since their OFF currentsmaintain a low value over a broad range of negative gate bias (see J. DeBaets, Van Calster, J. Capon, I De Rycke, H. De Smet, J. Doutreloingeand J. Vanfleteren, T. Fujisawa. H. Ogawa and H. Takatsu, in Thin FilmTransistor Technologies/1992, Y. Kuo, Editor, PV 92-24, page 296, TheElectrochemical Society Proceedings Series, Pennington N.J. (1992)).This type of protection is not operative in the embodiments of FIGS. 2and 4 since portions of the transistor channel near the contacts areeither shielded from the top gate by the overhang or source/drain metalor are not covered by the top gate.

Turning to the alternative embodiment of FIG. 7, the charge dissipationtransistors 15 have been eliminated. One approach to fabrication of thedevice embodiment of FIG. 7 is to eliminate the step of etching theinsulator vias through insulating layers 37 in FIGS. 2 and 3 so thatthere is no electrical connection made between upper gate 41 andtransistor 15. In this configuration, the generated charge collected byupper gate 41 is drained by the intrinsic leakage of energy absorbinglayer 43. Erasure can be enhanced by re-radiating the device with thetop electrode 45 grounded. The embodiment of FIG. 7 is more suitable tocapturing still images than for video rate applications.

In the embodiment of FIG. 8, the radiation-generated charge is clearedvia transistors 15 to the source lines 19 rather than to the drain lines39 as in the preferred embodiment of FIG. 1. The measured current ofeach pixel in the embodiment of FIG. 8 will contain a short transientmode of charge being cleared from the adjacent top gate 41. Thistransient can be eliminated or ignored by the current measuringcircuitry 21 such that only DC current is measured.

In the embodiment of FIGS. 7 and 8 like reference numerals identify thesame electrical and structural features discussed above with referenceto FIGS. 1-4.

Other embodiments and modifications of the invention are possible. Forexample, the bottom gate of the transistors 15 can be connected to thesource line 19 which can, in turn, be connected to a switch for changingthe potential from virtual ground to an ON state value (assuming thatthe transistors 15 are operating in enhancement mode, i.e. transistors15 are OFF with V_(G) =0). This allows a given row of pixels to besensed without clearing the adjacent row. Multiple measurements (withaveraging) can then be performed over all of the pixels 11 and theentire image can be cleared subsequently using the aforementioned sourceline switches.

According to another embodiment, instead of using a common drain for allof the TFT transistors, the drains can be connected to the bottom gatelines or connected to common rows. These modifications requireadditional mask levels for vias to the bottom gates 27, 29, or for anadditional level of metalization. All such modifications and embodimentsare believed to be within the sphere and scope of the present inventionas defined by the claims appended hereto.

The embodiments of the invention in which an exclusive property ofprivilege is claimed are defined as follows:
 1. An electromagneticradiation imaging device comprising:a) a substrate: b) a first pluralityof thin film transistors deposited on said substrate, each one of saidtransistors having a semiconductor channel, a lower gate electrodeunderlying said semiconductor channel for periodically enabling arespective row of said transistors, an upper gate electrode overlyingsaid semiconductor channel for regulating current flowing through saidsemiconductor channel when said respective row of said transistors isenabled, a drain electrode and a source electrode, each said drainelectrode of said plurality of thin film transistors beinginterconnected to form an output line, and each said source electrode ofsaid plurality of thin film transistors being interconnected to form adata line; c) an energy absorbing layer overlying said plurality of thinfilm transistors for generating charge in response to being exposed toelectromagnetic radiation; d) a top electrode connected to a source ofpotential, said top electrode overlying said energy absorbing layer suchthat a potential difference causes said charge to be collected on eachupper gate electrode thereby regulating said current flowing througheach semiconductor channel in proportion to intensity of saidelectromagnetic radiation; e) means connected to each said data line formeasuring said current and thereby detecting said intensity ofelectromagnetic radiation; and f) a second plurality of thin filmtransistors adjacent respective ones of said first plurality of thinfilm transistors and sharing said upper gate electrodes therewith fordischarging said charge collected on said upper gate electrodes aftersaid respective ones of said first plurality of thin film transistorshas been enabled.
 2. The electromagnetic radiation imaging device ofclaim 1, wherein each lower gate electrode and each semiconductorchannel are separated by a first dielectric layer and each upper gateelectrode and each semiconductor channel are separated by a seconddielectric layer.
 3. The electromagnetic radiation imaging device ofclaim 2, wherein said source and drain electrodes are deposited on saidfirst dielectric layer for contacting each semiconductor channel at thebottom thereof.
 4. The electromagnetic radiation imaging device of claim2, including a further dielectric layer intermediate said first andsecond dielectric layers, and wherein said source and drain electrodesare deposited on said further dielectric layer for contacting eachsemiconductor channel at the top thereof.
 5. The electromagneticradiation imaging device of claim 1, wherein said energy absorbing layeris fabricated from selenium for detecting x-rays.
 6. The electromagneticradiation imaging device of claim 1, wherein said energy absorbing layeris fabricated from an amorphous silicon PIN stack for detecting visiblelight.
 7. The electromagnetic radiation imaging device of claim 1,wherein each of said electrodes is fabricated from metal material. 8.The electromagnetic radiation imaging device of claim 1, wherein one ofsaid electrodes is fabricated from indium tin oxide.
 9. Theelectromagnetic radiation imaging device of claim 1, wherein said firstand second plurality of thin film transistors are fabricated from one ofamorphous silicon, polycrystaline silicon or cadmium selenide.
 10. Anelectromagnetic radiation imaging device comprising:a) a substrate; b) afirst plurality of thin film transistors deposited on said substrate,each one of said transistors having a first semiconductor channel, afirst lower gate electrode underlying said first semiconductor channelfor periodically enabling a respective row of said transistors, an uppergate electrode overlying said first semiconductor channel for regulatingcurrent flowing through said semiconductor channel when said respectiverow of said transistors is enabled, a first drain electrode and a firstsource electrode, each said first drain electrode of said firstplurality of thin film transistors being interconnected to form anoutput line, and each said first source electrode of said firstplurality of thin film transistors being interconnected to form a dataline; c) a second plurality of thin film transistors, each one of saidsecond plurality of transistors having a further semiconductor channelunderlying said upper gate electrode such that said upper gate electrodeof respective ones of said first plurality and said second plurality ofthin film transistors is shared, a further lower gate electrodeunderlying said further semiconductor channel for periodically enablinga respective row of said second plurality of thin film transistors, afurther source electrode connected to said upper gate electrode and afurther drain electrode connected to said output line, for dischargingcharge collected on said upper gate electrode after said respective rowsof said plurality of thin film transistors have been enabled; d) anenergy absorbing layer overlying said first plurality and said secondplurality of thin film transistors for generating charge in response tobeing exposed to electromagnetic radiation; e) a top electrode connectedto a source of potential, said top electrode overlying said energyabsorbing layer such that a potential difference causes said charge tobe collected on said upper gate electrode thereby regulating saidcurrent flowing through said first semiconductor channel in proportionto intensity of said electromagnetic radiation; and f) means connectedto each said data line for measuring said current and thereby detectingsaid intensity of electromagnetic radiation.
 11. The electromagneticradiation imaging device of claim 10, wherein said first and furtherlower gate electrodes and said first and further semiconductor channelsare separated by a first dielectric layer and said upper gate electrodeand said first and further semiconductor channels are separated by asecond dielectric layer.
 12. The electromagnetic radiation imagingdevice of claim 11, wherein said first and said further source and drainelectrodes are deposited on said first dielectric layer for contactingsaid first and said further semiconductor channels, respectively, at thebottom thereof.
 13. The electromagnetic radiation imaging device ofclaim 11, including a further dielectric layer intermediate said firstand second dielectric layers, and wherein said first and said furthersource and drain electrodes are deposited on said further dielectriclayer for contacting said first and said further semiconductor channels,respectively, at the top thereof.